Trace32 flash autosar9/23/2023 Configurable interrupt controller (INTC) with non-maskable interrupt (NMI).8 KB instruction cache (with line locking), configurable as 2- or 4-way.128 KB on-chip SRAM with standby functionality (32 KB) and ECC.2 MB on-chip flash memory with ECC and read-while-write (RWW).Up to 4 multiply and accumulate operations per cycle. Up to 2 integer or floating point instructions per cycle.Superscalar architecture with 2 execution units.Variable length instruction encoding (VLE).The device has two levels of memory hierarchy consisting of 8 KB of instruction cache, backed by a 128 KB on-chip SRAM and a 2 MB internal flash memory.įor development, the device includes a calibration bus that is accessible only when using the STMicroelectronics calibration tool. In addition to the Power Architecture technology, this core supports instructions for digital signal processing (DSP). The microcontroller's e200z4 host processor core is built on the Power Architecture technology and designed specifically for embedded applications. It is compatible with devices in ST's SPC56xx family and offers performance and capability above that of the SPC563M devices. This microcontroller is a 32-bit system-on-chip (SoC) device intended for use in mid-range engine control and automotive transmission control applications. SPC564A70L7:32-bit Power Architecture MCU for Automotive Powertrain Applications
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